ARC Software and Development Tools Selector Chart

• Reduce cost by optimizing die size, power, and performance
• Differentiate and future-proof by choosing and configuring only the features you need
• Increase productivity with automatic generation of SystemC models and RTL for co-design

• Quickly develop applications with 200 MHz+ speeds

• Simultaneously debug  hardware and software

• Save 6 man-months or more of development effort

• Avoid expense and schedule slips by creating 100% cycle accurate SystemC models of any SoC RTL
• Deliver 100% cycle accurate models of your IP to your customers

• Decrease power and boost productivity with CPF output from ARChitect IP Configurator for ARC Energy PRO products

• Improve efficiency with seamless integration of ARChitect output with all major EDA tool flows

• Immediately prototype with ARChitect IP Configurator outputs and FPGA flows

• Save on hardware memory costs – Compiler is optimized for smallest code size and speed
• Increase productivity with unparalled hardware and software visibility and profiling

• Efficiently debug and bring-up hardware boards
• Purchase from world-class vendors like Ashling, Corelis, Green Hills and Lauterbach

• Open source solution optimized for ARC IP
• Reduce risk with support from ARC

• Extend battery life through Energy PRO power management at the thread level and automatic DVFS
• Reduce cost compared to creating scheduler or RTOS from scratch

• Industry-standard OS for ARC subsystems and processors and with MMU
• Reduce risk with support from ARC

• Reuse existing software with ARC ports for Express Logic ThreadX, μITRON, μC/OS-II, CMX