Software & Tools

Overview of ARC® Software and Tools

Shorten Time-to-Market by 6 to 9 Months

With ARC's software and development tools, designer can “close the loop” faster, quickly iterating between IP configuration, simulation, assessment, and if required, re-configuration. To accelerate this process, developing hardware and software in parallel has been proven to shave anywhere from 6 to 9 months off a traditional 12-18 month development cycle while simultaneously reducing the risk of a re-spin. This risk of a re-spin is especially important where requirements change during development. Developing hardware and software in parallel and decreasing the time for each develop/debug/optimize cycle reduces product risk, allows for earlier product releases and permits the design team to respond to late requirements requests.

Benefits

ARC has integrated these innovative technologies into a comprehensive product suite that enables a clear Configure, Co-Design, Develop and Deploy product development process. Benifits:

Faster time-to-market – Parallelize hardware and software development and decrease development times
Lower development risk – Increase the number of develop/debug/optimize cycles to ensure your product meets your requirements
Differentiate & future proof – Add more features or respond to late feature requests with the schedule time gained

ARC Software and Development Tools Selector Chart

Function	Product	Benefits
Configure	ARChitect IP Configurator	Reduce cost by optimizing die size, power, and performance Differentiate and future-proof by choosing and configuring only the features you need Increase productivity with automatic generation of SystemC models and RTL for co-design
Co-Design	xISS Fast Instruction Set Simulator (ISS)	Quickly develop applications with 200 MHz+ speeds
Co-Design	xCAM Generator	Save 6 man-months or more of development effort
Hardware Development	Cadence Low Power Flow	Decrease power and boost productivity with CPF output from ARChitect IP Configurator
	EDA Flows from Synopsys, Mentor and Magma	Improve efficiency with seamless integration of ARChitect output with all major EDA tool flows
	FPGA Flows from Synplicity, Synopsys & Xilinx	Immediately prototype with ARChitect IP Configurator outputs and FPGA flows
Software Development	MetaWare Development Toolkit	Save on hardware memory costs using a compiler that is optimized for smallest code size and speed Increase productivity with unparalled hardware and software visibility and profiling
	JTAG Debuggers	Efficiently debug and bring-up hardware boards Purchase from world-class vendors like Ashling, Corelis, Green Hills and Lauterbach
	GNU Tools	Open source solution optimized for ARC IP Reduce risk with support from ARC
Deploy	MQX RTOS	Extend battery life through Energy PRO power management at the thread level and automatic DVFS Reduce cost compared to creating scheduler or RTOS from scratch
	Linux	Industry-standard OS for ARC subsystems and processors and with MMU Reduce risk with support from ARC
	Third-Party Operating Systems	Reuse existing software with ARC ports for Express Logic ThreadX, μITRON, μC/OS-II, CMX

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ARC® Codec Libraries

Enable Long-Term, Strategic Development and Planning of Multimedia SoCs

ARC’s codec libraries address the ever growing need for SoC designers to support more and more multimedia formats. The codec libraries provide access to current and future formats required for their applications. This simplifies long-term strategic planning of chip companies, allowing them to better meet the changing requirements of evolving consumer electronics devices.
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