Products
ARC® 750D Core
Best-in-Class Application Processor Core for High-End Embedded Operating Systems
The configurable ARC® 750D core is ideal for complex system-on-chips (SoCs) running Linux or other high-end operating systems. It is a complete application processor solution for home entertainment systems, portable devices such as smartphones and PDAs, automotive telematics systems, and many other information-based products.
Compared to ARM1136 and MIPS32 24Kc cores with similar configuration and speed, the ARC 750D core requires approximately half the die area and half the power. In addition, custom extensions may optionally be incorporated to achieve application performance levels unattainable with fixed architecture cores.
Benefits
Differentiate With Configurability
- Enable Linux applications with small size, low power and configurable architecture
- Choose only the features required; de-configure or add features as requirements change
- Create unique custom features through configurability and custom extensions
Differentiate With Performance
- Configurable memory architecture makes it ideal for Linux-based applications
- Accelerate signal processing algorithms with built-in DSP features
- Achieve 100-times performance improvements for critical routines with user-defined instruction and register extensions
Reduce Time to Market and Minimize Risk
- 150+ customers with 300+ million commercially proven customer chips shipping annually
- Complete development tools and design flow support, including industry-leading co-design
- Silicon-proven, pre-verified options cut design cycle time
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ARC 750D Characteristics
| Product Characteristics in 90nm Process* |
| Max Clock Frequency |
700 MHz |
| Power Consumption |
0.12 mW/MHz |
| Silicon Area |
0.53 mm˛ |
| *Frequency (worst case condition) is based on TSMC 90nm GT. Power (typical condition) and area are based on TSMC 90nm LP process. Data is for base configuration, placed and routed design (excluding RAM’s).
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ARC 750D Block Diagram
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Highlights
- A highly configurable architecture allows SoC designers to include only the processor features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
- User-defined instruction and register extensions deliver 5 - 100 times performance improvement of critical routines.
- Cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation.
- Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms.
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores.
- ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets.
- Inter-processor communication ISA support, multi-processor debug environment and flexible interfaces enable multi-core designs.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
- Delivered as synthesizable RTL source code (Verilog®), the ARC 750D core is fully compatible with industry standard design methodologies and tool flows.
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ARC® 750D Configurable Core Features
CPU Architecture
- 7-stage scalar, fully interlocked instruction pipeline
- Dynamic branch prediction
- Secure processing - Limited privileges for user tasks - Exception on illegal instruction
- Multi-processing support - Synchronization - Atomic exchange
- Single-cycle instruction CCM (Closely Coupled Memory), 8KB - 512KB
- Single-cycle data CCM, 8KB - 256KB
- Configurable instruction cache, 8KByte - 64KByte
- Configurable data cache, 8KByte - 64KByte
- Memory Management Unit (MMU)
- Up to 32, two level interrupts
ARCompact™ ISA
- 16- and 32-bit instructions for high code density
- No overhead for switching between
- Single-cycle instruction execution
- Up to 190 dual, single or zero operand instructions
- Up to 64 directly addressable core registers and 32 conditional execution codes
- Flexible addressing modes
Registers
- 32 entry register file in base processor, extendible to 60.
- Extendible registers may be special purpose, for wide data processing, data side effects, or data forwarding to other processing elements
- 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval
ARC FPX Floating Point Extensions
DSP Extensions
- 16- and 32-bit MUL and MAC instructions
- Parallel execution of MUL, MAC and other ALU operations
- Saturating arithmetic instructions
- Zero overhead loop support
ARC XY Advanced DSP Subsystem
- Full DSP performance using configurable banks of XY memory
- Eliminate DSP and logic blocks
- Consolidate development environment
- View more information on the ARC XY Subsystem
Power Management
- Sleep mode via software instruction
- High efficiency pipeline
- On-chip RAM controls
Host Interface/Debug Features
- Software and hardware breakpoints with cascadable triggers
- JTAG interface to host tools
- Debug host can access all registers and CPU memory
- Supported by leading debuggers including Green Hills Software and MetaWare®
System Interface
- Configurable ports comply with industry standard AMBA AHB, AMBA AXI, and BVCI
- Slave interfaces exposed for loading optional instruction and data CCMs
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