ARC International

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ARC® 600 Core Family

Configurable 32-Bit CPU/DSP Cores Deliver Smallest Area and Lowest Power in their Class


The ARC® 600 family of configurable cores is ideal for embedded control, computation and DSP tasks in system-on-chips (SoCs) for consumer, networking, automotive and many other markets. The core family is especially well suited to battery-operated and cost-sensitive products.


Benefits of the 600 Core Family


Lean

The configurable architecture of the ARC 600 family allows SoC designers to select only the processor features that are required for their specific application, achieving smaller die size and lower power than is possible with a fixed architecture core.

Efficient

SoC designers can optimize application efficiency by defining extensions to the ARC 600 architecture, providing higher application performance than can be achieved with a fixed core. Alternatively, frequency can be lowered, resulting in a lower power core.

Gets More Work Done

With both 32-bit RISC and full performance DSP in a single architecture, the ARC 600 family cores can perform more functions in an SoC than any other cores in their class, allowing designers to eliminate additional logic or DSP blocks, and simplify software.

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ARC 600 Core Applications


ARC 600 Core Family Roadmap

This roadmap is provided for review purposes only. It does not imply any commitment by ARC International concerning availability of future products.

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ARC® 600 Architecture


CPU Architecture

The ARC 600 32-bit architecture employs a highly efficient 5-stage pipeline, achieving 1.3 DMIPS/MHz. The architecture includes flexible memory options to address a wide range of processing needs. These include single-cycle Closely Coupled Memories (CCMs) for instructions and data, as well as configurable I-cache and D-cache, and a Memory Protection Unit (MPU). External access is via multiple 32-bit ports, including main memory, auxiliary registers and CCMs. BVCI , AHB and AXI configuration options are supported.

ARCompact™ ISA

Up to 40 percent improvement in code density can be achieved with the ARCompact 16-/32-bit ISA. 16- and 32-bit instructions are freely mixed by compilers without overhead.

Highly Configurable

ARC enables designers to add features they need and remove features they do not need for their individual application. Performance, size and power tradeoffs are quickly accomplished and the resulting optimized solution will invariably have smaller area and lower production cost than a fixed processor core. Custom configurations are created using the drag and drop GUI of ARC's ARChitect™ Processor Configurator tool.

The menu of configuration options includes:

  • ARC 600 DSP extensions, including 16- and 32-bit MAC and saturating arithmetic instructions
  • Type and size of caches
  • Interrupts
  • DSP features
  • Timers
  • Custom instruction extensions
  • Pre-Configured instruction extensions

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Customized Instruction Extensions


ARC also makes it possible for SoC designers to add custom instructions, creating a processor that is highly tuned for the specific application. Reduction of up to 100 times in the number of clock cycles required for inner loops or repetitive software can be achieved. The result is higher application performance and/or lower device frequency and lower power than is possible with a fixed instruction set. Custom instructions are created directly in SystemC or Verilog using ARC's Extension Instruction Automation tool suite and templates.

Powerful DSP Capabilities

The ARC 600 family provides true DSP on a RISC pipeline, with performance up to 500 MMACs per second in a 0.13m process.

  • ARC 600 DSP Extensions include 16- and 32-bit MAC, saturating arithmetic instructions, and additional extensions which accelerate common DSP calculations
  • ARC XY Advanced DSP extensions provide full DSP performance by adding configurable banks of XY memory

Floating Point Instructions

ARC FPX Floating Point Extensions add high performance single and double precision math instructions to most cores within the configurable ARC 600 core family. The ARC FPX extensions dramatically accelerate computations where data sets have a large dynamic range and when high precision is required.

  • Single and Double precision instructions
  • ARC MetaWare Math Library
  • IEEE 754 Standard for binary floating point arithmetic

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Software Development


ARC 600 Cores are Supported by the Industry's Leading Development Environments:


Modeling Tools

  • Instruction Set Simulators verify functionality of the code with execution speeds up to 200 MHz
  • Cycle Accurate Simulator provides full timing information for system-level modeling and for optimization of critical code

On-chip Debug Features

Each core's JTAG interface allows a debug host to set software breakpoints, examine or change memory and register values, and step through the target code. Optional hardware breakpoints can be added.

Operating Systems

The ARC 600 family is supported by industry standard operating system software from ARC and from third parties. Available ports include:

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Downloads

Product Briefs


ARC International pioneered configurable processor technology and is the leader with over 150+ customers worldwide who collectively ship more than 300 million ARC-Based™ chips annually.



Applications

Consumer products

  • Personal audio and image players
  • Digital still cameras
  • Cordless phones
  • Entry level cellular handsets
  • Handheld games and toys

Network devices

  • Broadband modems
  • Wireless LANs
  • VoIP terminals and gateways
  • Home gateways

Automotive control

  • Chassis and body systems
  • Mass storage products
  • Disk drives
  • DVD player

Imaging

  • Inkjet printers
  • Multi-function peripherals

Multi-core designs for networking applications

  • Storage area networks
  • Packet processing
  • Security accelerators
    TCP offload engines

Industrial control


8- and 16-bit microcontroller design upgrades


Deeply Embedded state machines