Products
ARC® 610D Core
Small, Low Power Embedded Core Combines 32-Bit CPU and Powerful DSP Features
The ARC® 610D processor is ideal for SoC applications that include conventional computation and signal processing algorithms. The core is designed for hard, real-time processing, where high speed and deterministic response are required.
Powerful and flexible DSP options enable the 610D core to perform more functions and eliminate separate logic or DSP blocks from the SoC. Optionally, custom instruction extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores.
Benefits
Differentiate With Configurability
- Extend battery life and reduce cost by choosing only the features required
- De-configure the ARC 610 to create the world's smallest, lowest-power licensable core
- Create unique custom features through configurability and custom extensions
Differentiate With Performance
- Accelerate signal processing algorithms with built-in DSP features
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores
- Achieve 100-times performance improvements for critical routines with user-defined instruction and register extensions
Reduce Time to Market and Minimize Risk
- 150+ customers with 300+ million commercially proven customer chips shipping annually
- Complete development tools and design flow support, including industry-leading co-design
- Silicon-proven, pre-verified options cut design cycle time
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ARC 610 Characteristics
| Product characteristics in 90nm process* | | Max Clock Frequency | 500 MHz | | Power Consumption | 0.03 mW/MHz | | Silicon Area | 0.16 mm˛ | | *Frequency (worst case condition) is based on TSMC 90nm GT. Power (typical condition) and area are based on TSMC 90nm LP process. Data is for base configuration, placed and routed design (excluding RAM’s).
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ARC 610 Block Diagram
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Highlights
- A highly configurable architecture allows SoC designers to include only the processor features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
- User-defined instruction and register extensions deliver 5 - 100 times performance improvement of critical routines.
- Cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation.
- ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit-only instruction sets.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
- Delivered as synthesizable RTL source code (Verilog®), the ARC 610 core is fully compatible with industry standard design methodologies and tool flows.
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ARC® 610D Configurable Core Features
CPU Architecture
- 5-stage instruction pipeline
- Static branch prediction
- 32-bit data, instruction and address buses
- Scoreboarded data memory pipeline to reduce data stalls
- Single-cycle instruction CCM (Closely Coupled Memory), 1KB - 512KB
- Single-cycle data CCM, 2KB – 256KB
- Configurable endianness
- Up to 32, two level interrupts
ARCompact™ ISA
- 16- and 32-bit instructions for high code density
- No overhead for switching between 16- and 32-bit
- Single-cycle instruction execution
- Up to 128 dual or single operand instruction codes available for user-defined extensions
- Up to 64 directly addressable core registers and 32 conditional execution codes
- Flexible addressing modes
Registers
- 16 or 32 entry register file in base processor, extendible to 60
- 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval
DSP Extensions
- 16- and 32-bit MUL and MAC instructions
- Parallel execution of MUL, MAC and other ALU operations
- Saturating arithmetic instructions
- Zero overhead loop support
ARC XY Advanced DSP Subsystem
- Full DSP performance using configurable banks of XY memory
- Eliminate DSP and logic blocks
- Consolidate development environment
- Includes ARC DSPlib with extensions such as: Dual FFT, Viterbi, CRC, 24x24MAC
- View more information on the ARC XY Subsystem
Power Management
- Sleep mode via software instruction
- Clock gating option
- High efficiency pipeline
- On-chip RAM controls
Host Interface/Debug Features
- Software and hardware breakpoints with cascadable triggers
- JTAG interface to host tools
- Debug host can access all registers and CPU memory
- Supported by leading debuggers including Green Hills Software and MetaWare®
System Interface
- Configurable port complies with industry standard AMBA or BVCI
- Slave interfaces exposed for loading optional instruction and data CCMs
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